The present invention relates in general to semiconductors, and more particularly to nonvolatile memory circuits.
Electrically erasable floating gate memories are semiconductor devices that store data as charges on the floating gates of storage transistors and retain the data after power is removed. The data is written by applying high voltage pulses to a word line of the memory to induce a charge flow to the transistor's floating gate. The charge flow controls a conduction threshold of the transistor to set a cell current that is sensed to read the stored data.
When prior art memory circuits are programmed, the high voltage pulses applied to one transistor can alter the charges stored in other transistors coupled to the same word line. As a result, the conduction thresholds are altered, which reduces cell margins and causes data to be read incorrectly. Hence, prior art programming methods result in a memory with reduced reliability.
Hence, a memory programming method is needed that increases reliability by maintaining high cell margins.